General

Scope

This document describes the design rules for IHPs SG13G2 SiGe BiCMOS technology.

List of Abbreviations

List of abbreviations used within this document

Abbreviation	Explanation
BiCMOS	Bipolar CMOS
HBT	Heterojunction Bipolar Transistor
IC	Integrated Circuit
IHP	Innovations for High Performance Microelectronics
MIM	Metal-Insulator-Metal
NMOS	Negative Channel Metal Oxide Semiconductor
PMOS	Positive Channel Metal Oxide Semiconductor
RD	Reference Document
SiGe	Silicon Germanium

Reference Documents

[RD 1] IHP SG13G2 Open Source Process Specification Rev. 1.2

Layer Table

This chapter is a documentation of IHP layers definition which is valid in all technologies.

Remark: Only the layers described in the following table are allowed to be used in layout designs. Do not use layers exclusively reserved for internal usage.

	drawing			Defines active regions in substrate, where transistors, diodes and/or capacitors will be fabricated
	pin			Activ pin layer
	mask			added to Active:drawing at mask generation
	filler			Activ filler layer
	nofill			Activ filler exclusion layer
	OPC			Activ outer OPC definition layer
	iOPC			Activ inner OPC definition layer
	noqrc			No parasitics extraction
	drawing			Defines active npn collector region
	OPC			BiWind OPC definition layer
	drawing			Defines polysilicon gates and interconnect
	pin			GatPoly pin layer
	filler			GatPoly filler layer
	nofill			GatPoly filler exclusion layer
	OPC			GatPoly outer OPC definition layer
	iOPC			GatPoly inner OPC definition layer
	noqrc			No parasitics extraction
	drawing			Defines 1-st metal contacts to Activ, GatPoly
	OPC			Cont OPC definition layer
	drawing			Defines areas to receive P+ source/drain implant
	block			Defines areas which do not receive S/D implants
	drawing			Defines 1-st metal interconnect
	pin			Metal1 pin layer
	mask			added to Metal1:drawing at mask generation
	filler			Metal1 filler layer
	nofill			Metal1 filler exclusion layer
	slit			Metal1 slit definition layer
	text			Text layer for Metal1, used for LVS
	OPC			Metal1 OPC definition layer
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Defines regions where passivation coating is removed
	pin			Passiv pin layer
	sbump			Defines passivation openings for solder bump bonding
	pillar			Defines passivation openings for copper pillar formation
	pdl			Plasma dicing line
	drawing			Defines 2-nd metal interconnect
	pin			Metal2 pin layer
	mask			added to Metal2:drawing at mask generation
	filler			Metal2 filler layer
	nofill			Metal2 filler exclusion layer
	slit			Metal2 slit definition layer
	text			Text layer for Metal2, used for LVS
	OPC			Metal2 OPC definition layer
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Defines npn base poly region
	pin			BasPoly pin layer
	drawing			Defines areas to receive P+ source/drain implant
	drawing			Reserved for internal LDMOS development
	drawing			surrounds areas were digital DRC is valid
	drawing			Defines 1-st metal to 2-nd metal contact
	drawing			Defines 1-st back-side metal interconnect
	pin			BackMetal1 pin layer
	mask			added to BackMetal1:drawing at mask generation
	filler			BackMetal1 filler layer
	nofill			BackMetal1 filler exclusion layer
	slit			BackMetal1 slit definition layer
	text			Text layer for BackMetal1, used for LVS
	OPC			BackMetal1 OPC definition layer
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Defines regions where passivation coating is removed
	drawing			Identifies resistor areas
	drawing			Identifies memory areas
	drawing			Identifies bipolar transistor areas
	drawing			Identifies inductor areas
	pin			IND pin layer
	text
	drawing			Defines non salicided Activ and GatPoly, BasPoly areas
	drawing			Defines 2-nd metal to 3-rd metal contact
	drawing			Defines 3-rd metal interconnect
	pin			Metal3 pin layer
	mask			added to Metal3:drawing at mask generation
	filler			Metal3 filler layer
	nofill			Metal3 filler exclusion layer
	slit			Metal3 slit definition layer
	text			Text layer for Metal3, used for LVS
	OPC			Metal3 OPC definition layer
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Defines the regions that receive P-Channel VT adjust, P-Channel Punch-Through and N-Well implants
	pin			NWell pin layer
	drawing			Defines bipolar sub collector and isolated NMOS devices
	pin			nBuLay pin Layer
	block			Defines areas where no nBuLay implant is allowed
	drawing			Defines npn emitter window
	OPC			EmWind OPC definition layer
	drawing			Defines deep collector regions
	drawing			Defines Metal-Insulator-Metal capacitor area
	drawing			Edge Seal definition layer, reserved for internal use only
	drawing			Substrate recognition layer for LVS
	text			Substrate recognition text for LVS
	drawing			Pad recognition layer
	pillar			Copper pillar pad recognition layer
	sbump			Solder bump pad recognition layer
	drawing			Thick Gate Oxide
	drawing			Reserved for internal LDMOS development
	drawing			Reserved for internal use
	pin			Pwell pin layer
	block			Defines areas where no well implants are allowed PWL:=NOT(NWell OR PWellBlock)
	drawing			Reserved for internal use
	drawing			Defines 3-rd metal to 4-th metal contact
	drawing			Defines 4-th metal interconnect
	pin			Metal4 pin layer
	mask			added to Metal4:drawing at mask generation
	filler			Metal4 filler layer
	nofill			Metal4 filler exclusion layer
	slit			Metal4 slit definition layer
	text			Text layer for Metal4, used for LVS
	OPC			Metal4 OPC definition layer
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Defines heat source for transistors
	drawing			Defines heat source for resistors
	drawing			Fluidic back side etch
	drawing			Defines npn emitter poly region and pnp base poly region
	drawing			Substrate recognition layer for LVS
	drawing			Excludes areas from design rule checking. Designs with NoDRC are rejected!
	drawing			Macrocell name, element text layer
	drawing			Defines 4-th metal to 5-th metal contact
	drawing			Defines 5-th metal interconnect
	pin			Metal5 pin layer
	mask			added to Metal5:drawing at mask generation
	filler			Metal5 filler layer
	nofill			Metal5 filler exclusion layer
	slit			Metal5 slit definition layer
	text			Text layer for Metal5
	OPC			Metal5 OPC definition layer
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Defines regions where special radiation hard design rules are applied
	drawing			Defines position of RFMEMS cap
	drawing			Well implant for varicap devices
	drawing			Via on top of interposer’s TopMetal2
	drawing			Metal connected to IntBondVia
	drawing			Via on top of device’s TopMetal2
	drawing			Metal connected to DevBondVia
	drawing			Deep trench from front side for plasma dicing approach
	drawing			Redistribution layer for metal wiring after chip IO
	drawing			1st graphene layer
	drawing			2nd graphene layer
	drawing			Deep via between TopMetal2 and AntMetal1
	drawing			Extra second-metal layer for antenna and passive integration
	drawing			GraphBot, GraphTop and GraphGat to GraphMetal1 or GraphMet1L contact
	drawing			Backend integrated Si waveguide
	filler			SiWG filler layer
	nofill			SiWG filler exclusion layer
	drawing			Si waveguide etching layer
	drawing			SiN waveguide etching layer
	drawing			Additional passivation for graphene structures
	drawing			Defines G3 npn emitter window
	drawing			Defines G3 HV npn emitter window
	drawing			Burried Layer with reduced dose for isolated NLDMOS
	drawing			Extraction recognition layer for special CMOS devices
	drawing			Passivation opening
	drawing			Reserved for future use
	pin			Polimide pin layer
	drawing			general device recognition shape for device extraction
	pin			General device pin recognition layer
	esd			ESD device recognition layer
	diode			Active diode recognition layer
	tsv			TSV device recognition layer
	iprobe			Current probe
	diffprb			Differential current probe
	pillar			Copper pillar pad recognition layer
	sbump			Solder bump pad recognition layer
	otp			OTP device recognition layer
	pdiode			Enables extraction of parasitic diodes
	mom			Metal-on-metal (MOM) capacitor recognition layer
	pcm			Process control structure recognition layer
	drawing			Defines additional collector opening in SG13 HBTs
	drawing			Graphene-metal standard interconnect
	filler			GraphMetal1 filler layer
	nofill			GraphMetal1 filler exclusion layer
	slit			GraphMetal1 slit definition layer
	OPC			Graphene-metal opc
	drawing			Graphene-metal lift-off interconnect
	filler			GraphMet1L filler layer
	nofill			GraphMet1L filler exclusion layer
	slit			GraphMet1L slit definition layer
	OPC			Graphene-metal lift-off opc
	drawing			Block tip and halo implants
	drawing			Dedicated pwell body for NLDMOS
	drawing			Dedicated nwell body for PLDMOS
	drawing			Reserved for internal LDMOS development
	drawing			Reserved for internal use
	drawing			Reserved for internal use
	drawing			Reserved for internal use
	drawing			Graphene GFET gate
	drawing			Backend integrated SiN waveguide
	filler			SiNWG filler layer
	nofill			SiNWG filler exclusion layer
	drawing			Dedicated to open Pads in RF-MEMS module
	drawing			Defines 3-rd (or 5-th) metal to TopMetal1 contact
	drawing			Defines 1-st thick TopMetal layer
	pin			TopMetal1 pin layer
	mask			added to TopMetal1:drawing at mask generation
	filler			TopMetal1 filler layer
	nofill			TopMetal1 filler exclusion layer
	slit			TopMetal1 slit definition layer
	text			Text layer for TopMetal1, used for LVS
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Dedicated PWell body for isolated NLDMOS
	drawing			used to mark net resistors
	pin			Defines polysilicon gates and interconnect
	drawing			used to mark net mim capacitors
	drawing			P-separation implat INLDMOS (internal use)
	drawing			Extra first-metal layer for antenna and passive integration
	drawing			Defines via between TopMetal1 and TopMetal2
	drawing			Defines 2-nd thick TopMetal layer
	pin			TopMetal2 pin layer
	mask			added to TopMetal2:drawing at mask generation
	filler			TopMetal2 filler layer
	nofill			TopMetal2 filler exclusion layer
	slit			TopMetal2 slit definition layer
	text			Text layer for TopMetal2
	noqrc			No parasitics extraction
	res			Wire resistor
	iprobe			Current probe
	diffprb			Differential current probe
	drawing			Sensor package ring
	drawing			Sensor recognition layer
	drawing			Arms of the Sensor
	drawing			Defines via between BiCMOS wafer and sensor
	drawing			Defines enclosed active transistor region
	drawing			Defines fluidic channel
	drawing			MEMRES dielectric layer
	drawing			Local Vias within RFM area
	drawing			ThinFilmRes (V) and recognition layer for RFMEMS
	drawing			Areas for integrated RF MEMS devices
	drawing			No parasitics extraction
	m2m3			No parasitics extraction in Metal2 and Metal3
	m2m4			No parasitics extraction in Metal2 and Metal4
	m2m5			No parasitics extraction in Metal2 and Metal5
	m2tm1			No parasitics extraction in Metal2 and TopMetal1
	m2tm2			No parasitics extraction in Metal2 and TopMetal2
	m3m4			No parasitics extraction in Metal3 and Metal4
	m3m5			No parasitics extraction in Metal3 and Metal5
	m3tm1			No parasitics extraction in Metal3 and TopMetal1
	m3tm2			No parasitics extraction in Metal3 and TopMetal2
	m4m5			No parasitics extraction in Metal4 and Metal5
	m4tm1			No parasitics extraction in Metal4 and TopMetal1
	m4tm2			No parasitics extraction in Metal4 and TopMetal2
	m5tm1			No parasitics extraction in Metal5 and TopMetal1
	m5tm2			No parasitics extraction in Metal5 and TopMetal2
	tm1tm2			No parasitics extraction in TopMetal1 and TopMetal2
	m1sub			No parasitics extraction in Metal1 and Substrate
	m2sub			No parasitics extraction in Metal2 and Substrate
	m3sub			No parasitics extraction in Metal3 and Substrate
	m4sub			No parasitics extraction in Metal4 and Substrate
	m5sub			No parasitics extraction in Metal5 and Substrate
	tm1sub			No parasitics extraction in TopMetal1 and Substrate
	tm2sub			No parasitics extraction in TopMetal2 and Substrate
	drawing			Sensor bottom via
	drawing			Sensor top via
	drawing			Through Silicon Via
	drawing			At this place the 1-st poly-Si layer (floating-gate) is etched before the 2-nd poly-Si layer (control-gate) is deposited
	drawing			This layer patterns the 2-nd poly-Si layer (control-gate)
	drawing			Defines areas where the Floating-gate is doped and the p-well of the flash-cells is formed
	drawing			EmWind layer for high voltage HBT
	drawing			For localized back side etch
	drawing			Reserved for internal use
	drawing			Exclude all metall filler
	drawing			Defines boundary of layour cells
	drawing			Support layer for layout data exchange (not used in mask preparation)
	pin			Pin layer of Exchange0
	text			Text layer of Exchange0
	drawing			Support layer for layout data exchange (not used in mask preparation)
	pin			Pin layer of Exchange1
	text			Text layer of Exchange1
	drawing			Support layer for layout data exchange (not used in mask preparation)
	pin			Pin layer of Exchange2
	text			Text layer of Exchange2
	drawing			Support layer for layout data exchange (not used in mask preparation)
	pin			Pin layer of Exchange3
	text			Text layer of Exchange3
	drawing			Support layer for layout data exchange (not used in mask preparation)
	pin			Pin layer of Exchange4
	text			Text layer of Exchange4
	drawing			Defines regions with alternative NWell implant to form isolated NWell

General Requirements

Grid Rules

• All rules are defined in microns [µm] by default if there is no other unit mentioned

• All features are on a drawing grid of 5 nm (0.005 µm)

• Shapes with acute angles <87° are not allowed on any layer

• Following layers are only allowed on 90, 180 degree angles: Cont, Via1, Via2, Via3, Via4, Vmim, TopVia1, TopVia2

• Following layers are only allowed on 90, 135, 180, 225, and 270 degree angles: GatPoly, Activ, Metal1, Metal2, Metal3, Metal4, Metal5, TopMetal1, TopMetal2

• Self-intersecting polygons must be avoided

• Design elements, which are snapped to grid must not violate any geometries in this document.

There are several layers which are not considered for mask generation. Offgrid and angle checks are not applied on the following layers: DigiBnd, RES, SRAM, IND, EdgeSeal, dfpad, HeatTrans, HeatRes, DigiSub, NoDRC, TEXT, RadHard, Flash, SMOS, Scribe, Recog, NoRCX, NoMetFiller

Forbidden Layers

Following layers are forbidden in designs submitted for all 0.13 µm technologies. Layout data containing these layers will be rejected from the tape-in procedure automatically. Since no waivers are granted, IHP recommends performing the online MPW Rejection Test (https://dk.ihp-microelectronics.com) at an early stage.

	drawing
	drawing
	drawing
	drawing
	drawing
	drawing
	drawing
	drawing
	drawing
	drawing
	drawing

Terminology

Design Rule Terminology

unrelated - two regions which do not touch each other

abut - two edges of two different layers touching each other

Rule check schematics.

Special Layer Configuration

Various rule definitions require derived layers instead of the original layers defined in chapter 2. The generation rules for the derived layers are described below.

	NOT ( OR ) OR
1	NOT ( OR ) OR
	((( ≥ 3.0 µm) sized by -1.0 µm/side) OR ) AND NOT
	( AND ) inside
	( AND ) inside
	AND
	AND
	AND
	over ( AND NOT )
	over (( AND ) inside )

Physical Layer Design Rules

NWell

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

NW.a & Min. width &

NW.a & Min. width & &

NW.b & Min. space or notch (same net). regions separated by less than this value will be merged. &

NW.b & Min. space or notch (same net). regions separated by less than this value will be merged. & &

NW.b1 & Min. width between regions (different net) (Note [nwell_n3]) &

NW.b1 & Min. width between regions (different net) (Note [nwell_n3]) & &

NW.c & Min. enclosure of not inside &

NW.c & Min. enclosure of not inside & &

NW.c1 & Min. enclosure of inside &

NW.c1 & Min. enclosure of inside & &

NW.d & Min. space to external not inside &

NW.d & Min. space to external not inside & &

NW.d1 & Min. space to external inside &

NW.d1 & Min. space to external inside & &

NW.e & Min. enclosure of NWell tie surrounded entirely by in not inside &

NW.e & Min. enclosure of NWell tie surrounded entirely by in not inside & &

NW.e1 & Min. enclosure of NWell tie surrounded entirely by in inside &

NW.e1 & Min. enclosure of NWell tie surrounded entirely by in inside & &

NW.f & Min. space to substrate tie in not inside &

NW.f & Min. space to substrate tie in not inside & &

NW.f1 & Min. space to substrate tie in inside &

NW.f1 & Min. space to substrate tie in inside & &

Notes

1. regions are allowed to cross well boundaries in some ESD protection layouts.

2. Substrate ties for internal logic are required due to p-silicon substrate.

3. A certain distance between and (see section 4.2) on different nets is required to prevent punchthrough due to different potentials.

dimensions (only rule variants without are shown in this figure)

PWell:block

layer is used to generate regions where both and implants are blocked.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

PWB.a & Min. width &

PWB.a & Min. width & &

PWB.b & Min. space or notch &

PWB.b & Min. space or notch & &

PWB.c & Min. space to unrelated &

PWB.c & Min. space to unrelated & &

PWB.d & Min. overlap of &

PWB.d & Min. overlap of & &

PWB.e & Min. space to ( not inside ) in &

PWB.e & Min. space to ( not inside ) in & &

PWB.e1 & Min. space to ( inside ) in &

PWB.e1 & Min. space to ( inside ) in & &

PWB.f & Min. space to ( not inside ) in &

PWB.f & Min. space to ( not inside ) in & &

PWB.f1 & Min. space to ( inside ) in &

PWB.f1 & Min. space to ( inside ) in & &

dimensions

nBuLay

defines regions with deep n-implants (deep nwell). This allows isolated nmos devices to be realized. Furthermore, may be generated automatically within (see 4.2) in order to reduce the resistance of the .

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

NBL.a & Min. width &

NBL.a & Min. width & &

NBL.b & Min. space or notch (same net) &

NBL.b & Min. space or notch (same net) & &

NBL.c & Min. width between regions (different net) (Note [nbulay_n1]) &

NBL.c & Min. width between regions (different net) (Note [nbulay_n1]) & &

NBL.d & Min. width between and (different net) (Note [nbulay_n1]) &

NBL.d & Min. width between and (different net) (Note [nbulay_n1]) & &

NBL.e & Min. space to unrelated &

NBL.e & Min. space to unrelated & &

NBL.f & Min. space to unrelated &

NBL.f & Min. space to unrelated & &

Notes

1. A certain space to and on different nets is required to prevent punchthrough due to different potentials. Please note that drawn as well as generated regions are considered (see 4.2).

dimensions

nBuLay:block

is used for generating structures, which are prevented from implant. Latchup prevention has to be carefully considered whenever layer is used (see 7.2).

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

NBL.a & Min. width &

NBL.a & Min. width & &

NBL.b & Min. space or notch &

NBL.b & Min. space or notch & &

NBL.c & Min. enclosure of &

NBL.c & Min. enclosure of & &

NBL.d & Min. space to unrelated &

NBL.d & Min. space to unrelated & &

dimensions

Activ

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Act.a & Min. width &

Act.a & Min. width & &

Act.b & Min. space or notch &

Act.b & Min. space or notch & &

Act.c & Min. drain/source extension &

Act.c & Min. drain/source extension & &

Act.d & Min. area (µm²) &

Act.d & Min. area (µm²) & &

Act.e & Min. enclosed area (µm²) &

Act.e & Min. enclosed area (µm²) & &

dimensions

Activ:filler

pattern are required in order to reduce layout sensitivity due to etching and CMP process steps.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

AFil.a & Max. width &

AFil.a & Max. width & &

AFil.a1 & Min. width &

AFil.a1 & Min. width & &

AFil.b & Min. space &

AFil.b & Min. space & &

AFil.c & Min. space to , &

AFil.c & Min. space to , & &

AFil.c1 & Min. space to &

AFil.c1 & Min. space to & &

AFil.d & Min. space to , &

AFil.d & Min. space to , & &

AFil.e & Min. space to &

AFil.e & Min. space to & &

AFil.g & Min. global density [%] &

AFil.g & Min. global density [%] & &

AFil.g1 & Max. global density [%] &

AFil.g1 & Max. global density [%] & &

AFil.g2 & Min. coverage ratio for any 800 x 800 µm² chip area [%] &

AFil.g2 & Min. coverage ratio for any 800 x 800 µm² chip area [%] & &

AFil.g3 & Max. coverage ratio for any 800 x 800 µm² chip area [%] &

AFil.g3 & Max. coverage ratio for any 800 x 800 µm² chip area [%] & &

AFil.i & Min. space to edges of &

AFil.i & Min. space to edges of & &

AFil.j & Min. and enclosure of inside &

AFil.j & Min. and enclosure of inside & &

Notes

1. layer can be used for filler pattern exclusion within specific device areas such as inductors or transformers as long as AFil.g2 and AFil.g3 are fulfilled. For larger sensitive areas it is recommended to minimize the conductivity of patterns by using , and .

dimensions

ThickGateOxide

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TGO.a & Min. extension over &

TGO.a & Min. extension over & &

TGO.b & Min. space between and outside thick gate oxide region &

TGO.b & Min. space between and outside thick gate oxide region & &

TGO.c & Min. extension over over &

TGO.c & Min. extension over over & &

TGO.d & Min. space between and over outside thick gate oxide region &

TGO.d & Min. space between and over outside thick gate oxide region & &

TGO.e & Min. space (merge if less than this value) &

TGO.e & Min. space (merge if less than this value) & &

TGO.f & Min. width &

TGO.f & Min. width & &

dimensions

GatPoly

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Gat.a & Min. width &

Gat.a & Min. width & &

Gat.a1 & Min. width for channel length of 1.2 V NFET &

Gat.a1 & Min. width for channel length of 1.2 V NFET & &

Gat.a2 & Min. width for channel length of 1.2 V PFET &

Gat.a2 & Min. width for channel length of 1.2 V PFET & &

Gat.a3 & Min. width for channel length of 3.3 V NFET &

Gat.a3 & Min. width for channel length of 3.3 V NFET & &

Gat.a4 & Min. width for channel length of 3.3 V PFET &

Gat.a4 & Min. width for channel length of 3.3 V PFET & &

Gat.b & Min. space or notch &

Gat.b & Min. space or notch & &

Gat.b1 & Min. space between unrelated 3.3 V over regions &

Gat.b1 & Min. space between unrelated 3.3 V over regions & &

Gat.c & Min. extension over (end cap) &

Gat.c & Min. extension over (end cap) & &

Gat.d & Min. space to &

Gat.d & Min. space to & &

Gat.e & Min. area (µm²) &

Gat.e & Min. area (µm²) & &

Gat.f & 45-degree and 90-degree angles for on area are not allowed &

Gat.f & 45-degree and 90-degree angles for on area are not allowed & &

Gat.g & Min. width for 45-degree bent shapes if the bend length is > 0.39 µm &

Gat.g & Min. width for 45-degree bent shapes if the bend length is > 0.39 µm & &

dimensions

GatPoly:filler

pattern are required in order to reduce layout sensitivity due to etching and CMP process steps.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

GFil.a & Max. width &

GFil.a & Max. width & &

GFil.b & Min. width &

GFil.b & Min. width & &

GFil.c & Min. space &

GFil.c & Min. space & &

GFil.d & Min. space to , , , , , &

GFil.d & Min. space to , , , , , & &

GFil.e & Min. space to , &

GFil.e & Min. space to , & &

GFil.f & Min. space to &

GFil.f & Min. space to & &

GFil.g & Min. global density [%] &

GFil.g & Min. global density [%] & &

GFil.i & Max. area (µm²) &

GFil.i & Max. area (µm²) & &

GFil.j & Min. extension over (end cap) &

GFil.j & Min. extension over (end cap) & &

Notes

1. layer can be used for filler pattern exclusion within specific device areas such as inductors or transformers.

dimensions

pSD

Defines regions which receive p+ implants. Typically used for source/drain implants, resistors and substrate ties.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

pSD.a & Min. width &

pSD.a & Min. width & &

pSD.b & Min. space or notch (Note [psd_n1]) &

pSD.b & Min. space or notch (Note [psd_n1]) & &

pSD.c & Min. enclosure of in &

pSD.c & Min. enclosure of in & &

pSD.c1 & Min. enclosure of in &

pSD.c1 & Min. enclosure of in & &

pSD.d & Min. space to unrelated in &

pSD.d & Min. space to unrelated in & &

pSD.d1 & Min. space to in &

pSD.d1 & Min. space to in & &

pSD.e & Min. overlap of at one position when forming abutted substrate tie (Note [psd_n2]) &

pSD.e & Min. overlap of at one position when forming abutted substrate tie (Note [psd_n2]) & &

pSD.f & Min. extension over at one position when forming abutted tie (Note [psd_n2]) &

pSD.f & Min. extension over at one position when forming abutted tie (Note [psd_n2]) & &

pSD.g & Min. or area (µm²) when forming abutted tie (Note [psd_n2]) &

pSD.g & Min. or area (µm²) when forming abutted tie (Note [psd_n2]) & &

pSD.i & Min. enclosure of PFET gate (thin gate oxide) &

pSD.i & Min. enclosure of PFET gate (thin gate oxide) & &

pSD.i1 & Min. enclosure of PFET gate (thick gate oxide) &

pSD.i1 & Min. enclosure of PFET gate (thick gate oxide) & &

pSD.j & Min. enclosure of NFET gate (thin gate oxide) &

pSD.j & Min. enclosure of NFET gate (thin gate oxide) & &

pSD.j1 & Min. enclosure of NFET gate (thick gate oxide) &

pSD.j1 & Min. enclosure of NFET gate (thick gate oxide) & &

pSD.k & Min. area (µm²) &

pSD.k & Min. area (µm²) & &

pSD.l & Min. enclosed area (µm²) &

pSD.l & Min. enclosed area (µm²) & &

pSD.m & Min. space to n-type poly resistors &

pSD.m & Min. space to n-type poly resistors & &

pSD.n & Min. enclosure of p-type poly resistors &

pSD.n & Min. enclosure of p-type poly resistors & &

Notes

1. regions separated by less than this value will be merged.

2. These rules are for abutted ties: An electrical connection from P+Activ to NWell tie (or N+ Activ to P-sub tie) is made through the source/drain silicide. For a good electrical connection rule pSD.g is important together with rule pSD.e or pSD.f (see Fig. 5.1).

dimensions

nSD:block

layer is used to generate regions where n+ S/D implants are blocked. The final mask data are generated by: nSD: = NOT (pSD OR nSD:block).

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

nSDB.a & Min. width &

nSDB.a & Min. width & &

nSDB.b & Min. space or notch &

nSDB.b & Min. space or notch & &

nSDB.c & Min. space to unrelated &

nSDB.c & Min. space to unrelated & &

nSDB.d & Min. overlap of (Note [nsdb_n1]) &

nSDB.d & Min. overlap of (Note [nsdb_n1]) & &

nSDB.e & Min. space to (Note [nsdb_n2]) &

nSDB.e & Min. space to (Note [nsdb_n2]) & &

Notes

1. and are allowed to overlap or to be line-on-line.

2. and do not overlap.

dimensions

EXTBlock

layer is used to generate regions where all tip and halo implants are blocked.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

EXT.a & Min. width &

EXT.a & Min. width & &

EXT.b & Min. space or notch &

EXT.b & Min. space or notch & &

EXT.c & Min. space to &

EXT.c & Min. space to & &

dimensions

SalBlock

is used to block salicidation of or source/drain areas.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Sal.a & Min. width &

Sal.a & Min. width & &

Sal.b & Min. space or notch &

Sal.b & Min. space or notch & &

Sal.c & Min. extension over or &

Sal.c & Min. extension over or & &

Sal.d & Min. space to unrelated or &

Sal.d & Min. space to unrelated or & &

Sal.d & Min. space to &

Sal.d & Min. space to & &

dimensions

Cont

This section describes design rules for square-shaped regions. All non-square shapes in layer are covered in section 5.15.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Cnt.a & Min. and max. width &

Cnt.a & Min. and max. width & &

Cnt.b & Min. space &

Cnt.b & Min. space & &

Cnt.b1 & Min. space in a contact array of more than 4 rows and more then 4 columns (Note [cnt_n1]) &

Cnt.b1 & Min. space in a contact array of more than 4 rows and more then 4 columns (Note [cnt_n1]) & &

Cnt.c & Min. enclosure of &

Cnt.c & Min. enclosure of & &

Cnt.d & Min. enclosure of &

Cnt.d & Min. enclosure of & &

Cnt.e & Min. on space to &

Cnt.e & Min. on space to & &

Cnt.f & Min. on space to &

Cnt.f & Min. on space to & &

Cnt.g & must be within or &

Cnt.g & must be within or & &

Cnt.g1 & Min. space to on &

Cnt.g1 & Min. space to on & &

Cnt.g2 & Min. overlap of on &

Cnt.g2 & Min. overlap of on & &

Cnt.h & must be covered with &

Cnt.h & must be covered with & &

Cnt.j & on over is not allowed &

Cnt.j & on over is not allowed & &

Notes

1. Cnt.b1 is only required in one direction. The distance of the other direction must be at least Cnt.b.

dimensions

ContBar

Any shape not being a square shape is considered a .

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

CntB.a & Min. and max. width &

CntB.a & Min. and max. width & &

CntB.a1 & Min. length &

CntB.a1 & Min. length & &

CntB.b & Min. space &

CntB.b & Min. space & &

CntB.b1 & Min. space with common run > 5 µm &

CntB.b1 & Min. space with common run > 5 µm & &

CntB.b2 & Min. space to &

CntB.b2 & Min. space to & &

CntB.c & Min. enclosure of &

CntB.c & Min. enclosure of & &

CntB.d & Min. enclosure of &

CntB.d & Min. enclosure of & &

CntB.e & Min. on space to &

CntB.e & Min. on space to & &

CntB.f & Min. on space to &

CntB.f & Min. on space to & &

CntB.g & must be within or &

CntB.g & must be within or & &

CntB.g1 & Min. space to on &

CntB.g1 & Min. space to on & &

CntB.g1 & Min. overlap of on &

CntB.g1 & Min. overlap of on & &

CntB.h & must be covered with &

CntB.h & must be covered with & &

CntB.h1 & Min. enclosure of &

CntB.h1 & Min. enclosure of & &

CntB.j & on over is not allowed &

CntB.j & on over is not allowed & &

dimensions

Metal1

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

M1.a & Min. width &

M1.a & Min. width & &

M1.b & Min. space or notch &

M1.b & Min. space or notch & &

M1.c & Min. enclosure of &

M1.c & Min. enclosure of & &

M1.c1 & Min. endcap enclosure of (Note [m1_n1]) &

M1.c1 & Min. endcap enclosure of (Note [m1_n1]) & &

M1.d & Min. area (µm²) &

M1.d & Min. area (µm²) & &

M1.e & Min. space of lines if, at least one line is wider than 0.3 µm and the parallel run is more than 1.0 µm &

M1.e & Min. space of lines if, at least one line is wider than 0.3 µm and the parallel run is more than 1.0 µm & &

M1.f & Min. space of lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm &

M1.f & Min. space of lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm & &

M1.g & Min. 45-degree bent width if the bent metal length is > 0.5 µm &

M1.g & Min. 45-degree bent width if the bent metal length is > 0.5 µm & &

M1.i & Min. space of lines of which at least one is bent by 45-degree &

M1.i & Min. space of lines of which at least one is bent by 45-degree & &

M1.j & Min. global density [%] &

M1.j & Min. global density [%] & &

M1.k & Max. global density [%] &

M1.k & Max. global density [%] & &

Notes

1. For contacts at corners at least one side must be treated as an endcap and for the other sides rule M1.c can be applied.

dimensions

Metal(n=2-5)

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Mn.a & Min. width &

Mn.a & Min. width & &

Mn.b & Min. space or notch &

Mn.b & Min. space or notch & &

Mn.c & Min. enclosure of &

Mn.c & Min. enclosure of & &

Mn.c1 & Min. endcap enclosure of (Note [mn_n1]) &

Mn.c1 & Min. endcap enclosure of (Note [mn_n1]) & &

Mn.d & Min. area (µm²) &

Mn.d & Min. area (µm²) & &

Mn.e & Min. space of lines if, at least one line is wider than 0.39 µm and the parallel run is more than 1.0 µm &

Mn.e & Min. space of lines if, at least one line is wider than 0.39 µm and the parallel run is more than 1.0 µm & &

Mn.f & Min. space of lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm &

Mn.f & Min. space of lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm & &

Mn.g & Min. 45-degree bent width if the bent metal length is > 0.5 µm &

Mn.g & Min. 45-degree bent width if the bent metal length is > 0.5 µm & &

Mn.i & Min. space of lines of which at least one is bent by 45-degree &

Mn.i & Min. space of lines of which at least one is bent by 45-degree & &

Mn.j & Min. global density [%] &

Mn.j & Min. global density [%] & &

Mn.k & Max. global density [%] &

Mn.k & Max. global density [%] & &

Notes

1. For vias at corners at least one side must be treated as an endcap and for the other sides rule Mn.c can be applied.

dimensions

Metal(n=1-5):filler

pattern are required in order to reduce layout sensitivity due to metal etching and CMP process steps.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

MFil.a1 & Min. width &

MFil.a1 & Min. width & &

MFil.a2 & Max. width &

MFil.a2 & Max. width & &

MFil.b & Min. space &

MFil.b & Min. space & &

MFil.c & Min. space to &

MFil.c & Min. space to & &

MFil.d & Min. space to &

MFil.d & Min. space to & &

MFil.h & Min. and coverage ratio for any 800 x 800 µm² chip area [%] &

MFil.h & Min. and coverage ratio for any 800 x 800 µm² chip area [%] & &

MFil.k & Max. and coverage ratio for any 800 x 800 µm² chip area [%] &

MFil.k & Max. and coverage ratio for any 800 x 800 µm² chip area [%] & &

Notes

1. A smaller coverage or larger filler exclusion area leads to smaller metal lines and higher sheet resistance. Sheet resistance of minimum width lines is increasing by 10% if metal coverage is lower than 30%.

2. must be generated prior to the tape out procedure. For sensitive areas of the circuit, designers should exclude using the or exclusion layer, or should place defined metal structures to prevent metal fill.

dimensions

Via1

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

V1.a & Min. and max. width &

V1.a & Min. and max. width & &

V1.b & Min. space &

V1.b & Min. space & &

V1.b1 & Min. space in an array of more than 3 rows and more then 3 columns (Note [v1_n1]) &

V1.b1 & Min. space in an array of more than 3 rows and more then 3 columns (Note [v1_n1]) & &

V1.c & Min. enclosure of &

V1.c & Min. enclosure of & &

V1.c1 & Min. endcap enclosure of (Note [v1_n2]) &

V1.c1 & Min. endcap enclosure of (Note [v1_n2]) & &

Notes

1. V1.b1 is only required in one direction. The distance of the other direction must be at least V1.b.

2. For at corners at least one side must be treated as an endcap and for the other sides rule V1.c can be applied.

dimensions

Via(n=2-4)

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Vn.a & Min. and max. width &

Vn.a & Min. and max. width & &

Vn.b & Min. space &

Vn.b & Min. space & &

Vn.b1 & Min. space in an array of more than 3 rows and more then 3 columns (Note [v1_n1]) &

Vn.b1 & Min. space in an array of more than 3 rows and more then 3 columns (Note [v1_n1]) & &

Vn.c & Min. enclosure of &

Vn.c & Min. enclosure of & &

Vn.c1 & Min. endcap enclosure of (Note [v1_n2]) &

Vn.c1 & Min. endcap enclosure of (Note [v1_n2]) & &

Notes

1. Vn.b1 is only required in one direction. The distance of the other direction must be at least Vn.b.

2. For at corners at least one side must be treated as an endcap and for the other sides rule Vn.c can be applied.

dimensions

TopVia1

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TV1.a & Min. and max. width &

TV1.a & Min. and max. width & &

TV1.b & Min. space &

TV1.b & Min. space & &

TV1.c & Min. enclosure of &

TV1.c & Min. enclosure of & &

TV1.d & Min. enclosure of &

TV1.d & Min. enclosure of & &

dimensions

TopMetal1

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TM1.a & Min. width &

TM1.a & Min. width & &

TM1.b & Min. space or notch &

TM1.b & Min. space or notch & &

TM1.c & Min. global density [%] &

TM1.c & Min. global density [%] & &

TM1.d & Max. global density [%] &

TM1.d & Max. global density [%] & &

dimensions

TopMetal1:filler

pattern are required in order to reduce layout sensitivity due to metal etching and CMP process steps.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TM1Fil.a & Min. width &

TM1Fil.a & Min. width & &

TM1Fil.a1 & Max. width &

TM1Fil.a1 & Max. width & &

TM1Fil.b & Min. space &

TM1Fil.b & Min. space & &

TM1Fil.c & Min. space to &

TM1Fil.c & Min. space to & &

TM1Fil.d & Min. space to &

TM1Fil.d & Min. space to & &

dimensions

TopVia2

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TV2.a & Min. and max. width &

TV2.a & Min. and max. width & &

TV2.b & Min. space &

TV2.b & Min. space & &

TV2.c & Min. enclosure of &

TV2.c & Min. enclosure of & &

TV2.d & Min. enclosure of &

TV2.d & Min. enclosure of & &

dimensions

TopMetal2

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TM2.a & Min. width &

TM2.a & Min. width & &

TM2.b & Min. space or notch &

TM2.b & Min. space or notch & &

TM2.bR & Min. space of lines if, at least one line is wider than 5.0 µm and the parallel run is more than 50.0 µm (Note [tm2_n1], [tm2_n2]) &

TM2.bR & Min. space of lines if, at least one line is wider than 5.0 µm and the parallel run is more than 50.0 µm (Note [tm2_n1], [tm2_n2]) & &

TM2.c & Min. global density [%] &

TM2.c & Min. global density [%] & &

TM2.d & Max. global density [%] &

TM2.d & Max. global density [%] & &

Notes

1. Violations can cause potential issues with TAPEs during backgrinding.

2. Not checked within regions.

dimensions

TopMetal2:filler

pattern are required in order to reduce layout sensitivity due to metal etching and CMP process steps.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TM2Fil.a & Min. width &

TM2Fil.a & Min. width & &

TM2Fil.a1 & Max. width &

TM2Fil.a1 & Max. width & &

TM2Fil.b & Min. space &

TM2Fil.b & Min. space & &

TM2Fil.c & Min. space to &

TM2Fil.c & Min. space to & &

TM2Fil.d & Min. space to &

TM2Fil.d & Min. space to & &

dimensions

Passiv

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Pas.a & Min. width &

Pas.a & Min. width & &

Pas.b & Min. space or notch &

Pas.b & Min. space or notch & &

Pas.c & Min. enclosure of (Note [pas_n1]) &

Pas.c & Min. enclosure of (Note [pas_n1]) & &

Notes

1. Not checked outside of sealring (edge-seal-passive)

dimensions

Device Layout Rules

Bipolar Design Rules

Bipolar design rules are not disclosed due to IP reasons. Additional layers will be added during the tape out procedure for mask generation. Changing the given layouts may result in catastrophic device malfunction. The IHP library provides a number of predefined devices shown in the follow sections. Do not modify these layouts/abstracts.

Strict design rule: Do not flatten the HBT layout cells and do not place any shapes, except metal for connections, in bipolar regions. Use pins on given metals to connect base, emitter and collector with corresponding metal shapes. Any modification in bipolar transistor results in non-working device.

Device recognition: For device recognition layer in combination with TEXT labels and layer combinations are used for device recognition.

Pre-defined Transistor Layouts

Device	Emitter width	Parameter	Comment
npn13G2	\(\mat hrm{W_E=0.07u}\)	\(\mat hrm{L_E=0.9u}\), \(\mathrm{ N_x=1\dots10}\), :math: mathrm{A_E=N_ xleft(0.07ucd ot L_Eright)}	math mathrm{L_E}: emitter length, :math: mathrm{A_E}: emitter area,:math: mathrm{N_x}: number of emitters in a row
npn13G2L	\(\mat hrm{W_E=0.07u}\)	:math :mathrm{L_E=1 .0udots2.5u}, \(\mathrm {N_x=1\dots4}\), :math: mathrm{A_E=N_ xleft(0.07ucd ot L_Eright)}	math mathrm{L_E}: emitter length, :math: mathrm{A_E}: emitter area,:math: mathrm{N_x}: number of emitters in a row
npn13G2V	\(\mat hrm{W_E=0.12u}\)	:math :mathrm{L_E=1 .0udots5.0u}, \(\mathrm {N_x=1\dots8}\), :math: mathrm{A_E=N_ xleft(0.12ucd ot L_Eright)}	math mathrm{L_E}: emitter length, :math: mathrm{A_E}: emitter area,:math: mathrm{N_x}: number of emitters in a row

Schematic Cross-section

Schematic cross-section of the SiGe:C hetero bipolar transistor

Design Rules

The is formed by and ring.

The following rules do not apply: nSDB.e

General Design Rules

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

npnG2.a & NPN Substrate-Tie = AND &

npnG2.a & NPN Substrate-Tie = AND & &

npnG2.b & must enclose &

npnG2.b & must enclose & &

npnG2.c & enclosure of inside &

npnG2.c & enclosure of inside & &

npnG2.d & Min. unrelated , , , , space to &

npnG2.d & Min. unrelated , , , , space to & &

npnG2.d1 & Min. unrelated space to &

npnG2.d1 & Min. unrelated space to & &

npnG2.d2 & Min. unrelated space to &

npnG2.d2 & Min. unrelated space to & &

npnG2.e & Min. unrelated space to &

npnG2.e & Min. unrelated space to & &

npnG2.f & are allowed to overlap each other &

npnG2.f & are allowed to overlap each other & &

Device Related Design Rules

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

npn13G2.a & Min. and max. emitter length &

npn13G2.a & Min. and max. emitter length & &

npn13G2.bR & Max. recommended total number of emitters per chip &

npn13G2.bR & Max. recommended total number of emitters per chip & &

npn13G2L.a & Min. emitter length &

npn13G2L.a & Min. emitter length & &

npn13G2L.b & Max. emitter length &

npn13G2L.b & Max. emitter length & &

npn13G2L.cR & Max. recommended total number of emitters per chip &

npn13G2L.cR & Max. recommended total number of emitters per chip & &

npn13G2V.a & Min. emitter length &

npn13G2V.a & Min. emitter length & &

npn13G2V.b & Max. emitter length &

npn13G2V.b & Max. emitter length & &

npn13G2V.cR & Max. recommended total number of emitters per chip &

npn13G2V.cR & Max. recommended total number of emitters per chip & &

HBT dimensions.

Rsil

Rsil represents the salicided n+ doped resistor.

Device recognition: Rsil = +

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Rsil.a & Min. width &

Rsil.a & Min. width & &

Rsil.b & Min. space to &

Rsil.b & Min. space to & &

Rsil.c & Min. extension over &

Rsil.c & Min. extension over & &

Rsil.d & Min. space to &

Rsil.d & Min. space to & &

Rsil.e & Min. enclosure of &

Rsil.e & Min. enclosure of & &

Rsil.f & Min. length &

Rsil.f & Min. length & &

Notes

1. represents the resistor definition layer and is required for back annotation.

dimensions

Rppd

Rppd represents the unsalicided p+ doped resistor.

Device recognition: Rppd = + +

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Rppd.a & Min. width &

Rppd.a & Min. width & &

Rppd.b & Min. enclosure of &

Rppd.b & Min. enclosure of & &

Rppd.c & Min. and max. space to &

Rppd.c & Min. and max. space to & &

Rppd.d & Min. enclosure of &

Rppd.d & Min. enclosure of & &

Rppd.e & Min. length &

Rppd.e & Min. length & &

dimensions

Rhigh

Rhigh represents an unsalicided partial compensated low n-doped resistor.

Device recognition: Rhigh = + + +

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Rhi.a & Min. width &

Rhi.a & Min. width & &

Rhi.b & and are identical (Note [rhigh_n1]) &

Rhi.b & and are identical (Note [rhigh_n1]) & &

Rhi.c & Min. and enclosure of &

Rhi.c & Min. and enclosure of & &

Rhi.d & Min. and max. space to &

Rhi.d & Min. and max. space to & &

Rhi.e & Min. enclosure of &

Rhi.e & Min. enclosure of & &

Rhi.f & Min. length &

Rhi.f & Min. length & &

Notes

1. is only permitted within resistors. Apart from that, is generated automatically (see section 4.2).

dimensions

nmosi and nmosiHV

Device recognition: nmosi is recognized as an nmos device. The difference of nmosi and nmosiHV is given by . There are special device construction rules for this substrate isolated nmos device. These rules will only be tested inside a closed ring of AND .

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

nmosi.b & Min. enclosure of (Note [nmosi_n1]) &

nmosi.b & Min. enclosure of (Note [nmosi_n1]) & &

nmosi.c & Min. space to &

nmosi.c & Min. space to & &

nmosi.d & Min. width forming an unbroken ring around any (Note [nmosi_n2]) &

nmosi.d & Min. width forming an unbroken ring around any (Note [nmosi_n2]) & &

nmosi.e1 & A separate Iso-PWell contact unabutted to a nmosi device is not allowed &

nmosi.e1 & A separate Iso-PWell contact unabutted to a nmosi device is not allowed & &

nmosi.e2 & nmosi unabutted to an Iso-PWell-Activ tie is not allowed &

nmosi.e2 & nmosi unabutted to an Iso-PWell-Activ tie is not allowed & &

nmosi.f & Min. width to separate ptap in nmosi &

nmosi.f & Min. width to separate ptap in nmosi & &

nmosi.g & Min. overlap of over &

nmosi.g & Min. overlap of over & &

Notes

1. Iso-PWell-Activ = AND AND

2. NWell-nBuLay = AND

3. NWell which is used as a ring for isolated PWell and carries active p-mos devices has to be carefully layed out in order to prevent latch up.

4. Recommendation: 1 mimimum PWell contact per 50 µm². To calculate voltage drops in PWell consider an average sheet resistance of 3 kΩ.

5. Recommendation: Use ptapsb Pcell to ensure proper isolated PWell connection. An example can be found in Cadence PDK’s example library.

isolbox

The isolbox structure is used to generate PWell regions isolated from the global substrate. This enables the realization of substrate isolated nmos transistors or resistors. We recommend to use only pcell offered via PDK by IHP. The pins “isosub” and “bn” are not part of the layout pcell and have to be placed manually in order to give designer more flexibility.

Device recognition: isolbox = TEXT “isolbox” within ( enclosed by )

a) Cross-section and b) top view of the isolbox device. (* These layers are inherently derived from drawing layers.)

Schottky diode

Device recognition: schottky_nbl1 = enclosed by ( and and and not )

The following rules do not apply: NW.c1, NW.e1, PWB.f1, CntB.a, LU.d

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Sdiod.a & Min. and max. enclosure of &

Sdiod.a & Min. and max. enclosure of & &

Sdiod.b & Min. and max. enclosure of &

Sdiod.b & Min. and max. enclosure of & &

Sdiod.c & Min. and max. enclosure of &

Sdiod.c & Min. and max. enclosure of & &

Sdiod.d & Min. and max. width inside &

Sdiod.d & Min. and max. width inside & &

Sdiod.e & Min. and max. length inside &

Sdiod.e & Min. and max. length inside & &

dimensions.

ESD Protection Devices

For ESD protection of the chip, special clamp devices are provided. Please refer to the ESD documents for details about protection level. Also note that it is recommended to have I/O MOS devices with channel length of at least 0.36 µm.

nmoscl_2

Clamp device for limiting supply voltage.

Device recognition: nmoscl_2 = TEXT “nmoscl_2” within

Following rules do not apply: nmosi.e, Gat.a3

nmoscl_4

Clamp device for limiting supply voltage.

Device recognition: nmoscl_4 = TEXT “nmoscl_4” within

Following rules do not apply: nmosi.e, Gat.a3

scr1

Device recognition: scr1 = TEXT “scr1” within

Following rules do not apply: nmosi.c, nmosi.g, LU.d, Gat.a

Pad Dimensions

Device recognition: Pad = ( + + ) +

Pad rules are tested only within recognition layer. Pad rules are only tested on metal structures which are on same net as . The following design rules must be also applied to solder bump pads and Cu pillar pads.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Pad.aR & Min. recommended width &

Pad.aR & Min. recommended width & &

Pad.a1 & Max. width &

Pad.a1 & Max. width & &

Pad.bR & Min. recommended space &

Pad.bR & Min. recommended space & &

Pad.d & Min. space to &

Pad.d & Min. space to & &

Pad.dR & Min. recommended to space (Note [pad_n1]) &

Pad.dR & Min. recommended to space (Note [pad_n1]) & &

Pad.d1R & Min. recommended to (inside chip area) space &

Pad.d1R & Min. recommended to (inside chip area) space & &

Pad.eR & Min. recommended , , exit width &

Pad.eR & Min. recommended , , exit width & &

Pad.fR & Min. recommended , , exit length &

Pad.fR & Min. recommended , , exit length & &

Pad.gR & (within ) enclosure of &

Pad.gR & (within ) enclosure of & &

Pad.i & without not allowed &

Pad.i & without not allowed & &

Pad.jR & No devices under allowed (Note [pad_n2]) &

Pad.jR & No devices under allowed (Note [pad_n2]) & &

Pad.kR & under not allowed (Note [pad_n3]) &

Pad.kR & under not allowed (Note [pad_n3]) & &

Notes

1. Distance of opening to strongly depends on bonding procedure. For flip chip bonding via solder bumps (see section 6.9.1) or copper pillars (see section 6.9.2) or manual bonding a bigger distance may be required. We strongly recommend 25 μm distance for wedge-wedge wire bonding.

2. Components under pads can be damaged by mechanical stress.

3. may be damaged during packaging process, we recommend not to use them below .

Pad dimensions.

Solder Bump Rules

These rules are valid within pads used for solder bumping and flip chip assembling. These pad rules are valid for 60 μm passive opening and 80 μm bump ball size. Bump ball standard is PacTech SAC305 (SnAgCu).

We recommend to use Solder Bump option in Pcell provided in the PDK.

For different geometries refer to design rule manual of our partner PacTech or the design rule manual of your specific bumping provider.

Device recognition: SBumpPad = +

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Padb.a & size &

Padb.a & size & &

Padb.b & Min. space &

Padb.b & Min. space & &

Padb.c & Min. (within ) enclosure of &

Padb.c & Min. (within ) enclosure of & &

Padb.d & Min. space to &

Padb.d & Min. space to & &

Padb.e & Min. pitch (Note [solder_n1]) &

Padb.e & Min. pitch (Note [solder_n1]) & &

Padb.f & Allowed passivation opening shape (Note [solder_n1]) &

Padb.f & Allowed passivation opening shape (Note [solder_n1]) & &

Notes

1. Underlying may have a different shape. This rule is not checked during DRC.

Pad dimensions for solder bumping process.

Copper Pillar Rules

These rules are valid within pads used for assembly with copper pillars. The given pad rules are valid for a number of different geometries offered by our partner PacTech given in table 6.1.

Important: Please note that pad opening may have an impact on final testing. If the passivation openings are too small, wafer-level testing may be prevented because the pad metal cannot be sufficiently contacted.

We recommend to use Solder Bump option in Pcell provided in the PDK.

Device recognition: CuPillarPad = +

* Thickness of optional SnAg cap after reflow at peak temp 260 degree C would be higher than that of after plating/ before reflow in the factor of 1.4 - 1.7, depending on the SnAg height as well.

Copper pillar layer stack with and without optional SnAg cap.

For different geometries than listed in table 6.1, refer to the design rule manual of our partner PacTech or the design rule manual of your specific bumping provider.

The following table defines design rules for PacTech’s copper pillar option with minimum passivation opening, copper pillar height and copper pillar pitch.

Valid pad geometries and design rules for Cu pillars.

Passiv opening	35	40	45	Padc.a
Opening spacing				Padc.b
Opening enclosure				Padc.c
CuPillarPad pitch				Padc.e
Cu pillar height	± 7	± 7	± 7
Cu pillar diameter	± 3	± 3	± 3
Cu height (A)	± 2	± 2	± 2
SnAg height* (B)	± 1	± 1	± 2

Notes

1. Passivation openings highlighted in green are suited for on-wafer measurements

2. Pads with passivation openings of 45 μm and 55 μm are suited for PCB applications. Minimum recommended pitch 250 μm; recommended standard pitch 500 μm.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Padc.a & size &

Padc.a & size & &

Padc.b & Min. space &

Padc.b & Min. space & &

Padc.c & Min. (within ) enclosure of &

Padc.c & Min. (within ) enclosure of & &

Padc.d & Min. space to &

Padc.d & Min. space to & &

Padc.e & Min. pitch (Note [pillar_n1]) &

Padc.e & Min. pitch (Note [pillar_n1]) & &

Padc.f & Allowed passivation opening shape (Note [pillar_n1]) &

Padc.f & Allowed passivation opening shape (Note [pillar_n1]) & &

Notes

1. Underlying may have a different shape. This rule is not checked during DRC.

Pad dimensions for copper pillar process.

Sealring

A sealring is an uninterrupted ring of metal and via layers. The purpose of the sealring is to reduce the effects of mechanical stress on the circuit that occurs during dicing of various chips. The sealring must be enclosed by an unbrokend ring of . Figure 6.8 shows distance between and the sealring boundary (30 μm) and the passivation opening. Please be aware that corresponding standard metal and via rules are not checked within regions.

Device recognition:

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Seal.a & Min. , , , , width &

Seal.a & Min. , , , , width & &

Seal.b & Min. space to , , , , &

Seal.b & Min. space to , , , , & &

Seal.c & ring width &

Seal.c & ring width & &

Seal.c1 & ring width &

Seal.c1 & ring width & &

Seal.c2 & ring width &

Seal.c2 & ring width & &

Seal.c3 & ring width &

Seal.c3 & ring width & &

Seal.d & Min. enclosure of , , , ring &

Seal.d & Min. enclosure of , , , ring & &

Seal.e & Min. ring width outside of sealring &

Seal.e & Min. ring width outside of sealring & &

Seal.f & Min. ring outside of sealring space to , , , &

Seal.f & Min. ring outside of sealring space to , , , & &

Seal.k & Min. 45-degree corner length (Note [seal_n1]) &

Seal.k & Min. 45-degree corner length (Note [seal_n1]) & &

Seal.l & No structures outside sealring boundary allowed &

Seal.l & No structures outside sealring boundary allowed & &

Seal.m & Only one sealring per chip allowed (Note [seal_n1]) &

Seal.m & Only one sealring per chip allowed (Note [seal_n1]) & &

Notes

1. Not checked during DRC

EdgeSeal and Sealring dimensions.

MIM

Metal-Insulator-Metal (MIM) capacitors are formed by a thin dielectric layer and conductor placed between , and .

Within capacitor layer can be used instead of . Some EDA tools cannot distinguish between interconnects and electrical components which are formed by the same conductive layers. Within the MIM device, can be replaced with to prevent false short circuit detection.

Device recognition: MIM capacitor = +

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

MIM.a & Min. width &

MIM.a & Min. width & &

MIM.b & Min. space &

MIM.b & Min. space & &

MIM.c & Min. enclosure of &

MIM.c & Min. enclosure of & &

MIM.d & Min. enclosure of &

MIM.d & Min. enclosure of & &

MIM.e & Min. space to &

MIM.e & Min. space to & &

MIM.f & Min. area per MIM device (µm²) &

MIM.f & Min. area per MIM device (µm²) & &

MIM.g & Max. area per MIM device (µm²) &

MIM.g & Max. area per MIM device (µm²) & &

MIM.gR & Max. recommended total area per chip (µm²) &

MIM.gR & Max. recommended total area per chip (µm²) & &

MIM.h & must be over &

MIM.h & must be over & &

dimensions

Inductors

In order to verify a custom inductor in the LVS check, additional layers must be added to the actual inductor layout (see Fig. 6.10). The inductor must be completely enclosed by the layer. To define the connection points, rectangles in layer must be placed on the inductor metal. The connection points must touch the edge of the layer and contain a pre-defined text label in layer . These text labels are “LA” and “LB” for inductors with two connections or “LA”, “LB” and “LC” for inductors with three connections.

Parasitic extraction of metal lines is excluded from inductors defined by this procedure. Within this layer there is by default no filler generation.

Following rules will not be checked within this layer: metal slit rules, AFil.g2, MFil.h, TM2.bR

Custom inductor connection method.

Special Rules

Antenna Rules

The antenna effect occurs when metal layers on a chip are etched during the semiconductor manufacturing process. As the metal layers are etched, the remaining metal traces collect charge during the etching process. When these metal traces discharge, it can lead to damage or unwanted changes in the properties of the connected devices.

The design rules related to unprotected devices are determined by using gate leakage current (shift of 10 % for nominal devices) as failure criterion.

Antenna Rules are not checked by default. Antenna rule checking must be switched on separately.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Ant.a & Max. ratio of over field oxide area to connected area &

Ant.a & Max. ratio of over field oxide area to connected area & &

Ant.b & Max. ratio of cumulative metal area (from to ) to connected area (without protection diode) &

Ant.b & Max. ratio of cumulative metal area (from to ) to connected area (without protection diode) & &

Ant.c & Max. ratio of area to connected area &

Ant.c & Max. ratio of area to connected area & &

Ant.d & Max. ratio of cumulative via area (from to ) to connected area (without protection diode) &

Ant.d & Max. ratio of cumulative via area (from to ) to connected area (without protection diode) & &

Ant.e & Max. ratio of cumulative metal area (from to ) to connected area (with protection diode) &

Ant.e & Max. ratio of cumulative metal area (from to ) to connected area (with protection diode) & &

Ant.f & Max. ratio of cumulative via area (from to ) to connected area (with protection diode) &

Ant.f & Max. ratio of cumulative via area (from to ) to connected area (with protection diode) & &

Ant.g & Size of protection diode (µm²) (Note [antenna_n4]) &

Ant.g & Size of protection diode (µm²) (Note [antenna_n4]) & &

Notes

1. The rules apply for both types of oxide.

2. Vn_area = cumulative area Cont, Via1 to TopVia2

3. Via_area = cumulative area Via1 to TopVia2

4. PDarea (µm²) = 0.02 x (Vn_area / (GatPoly over Activ)_area)

Cumulated area ratio calculation example.

\[\mathrm{AreaRatio\left(G1\right)=\frac{Area\{M1\left(i\right)\}+Area\{M2\left(i\right)\}}{Area\{G1\}}+\frac{Area\{M3\left(i\right)\}}{Area\{G1\}+Area\{G2\}+Area\{G3\}}}\]

\[\mathrm{AreaRatio\left(G2\right)=\frac{Area\{M1\left(ii\right)\}}{Area\{G2\}}+\frac{Area\{M2\left(ii\right)\}}{Area\{G2\}+Area\{G3\}}+\frac{Area\{M3\left(i\right)\}}{Area\{G1\}+Area\{G2\}+Area\{G3\}}}\]

Usage of stacked vias to avoid antenna area ratio violations. Please note that this figure is only an example. The stacked via method can be applied up to .

Recommendations

• To get DRC clean layouts it is recommended to connect the antenna node to the output of the driver at low metal level to reduce the antenna area or connect the antenna node to a diode.

• To get DRC clean layouts it is recommended to use stacked vias to connect large metal or via areas as shown in Fig. 7.2.

• To protect the gate of an isolated nMOS transistors it is recommended to place the antenna-protection diode in a separate (non isolated) p-body region.

• For applications which are especially sensitive to \(\mathrm{V_t}\) variation or mismatch (sense amplifers, certain analog circuits, etc.), each gate should be tied directly to an nSD/PWell or pSD/NWell diode in Metal1.

Latch-up Guidelines

Latch-up is an undesirable phenomenon in integrated circuit (IC) design that can lead to the inadvertent creation of a low-impedance path between the power supply rails or any other regions forming a parasitic thyristor. The effect is trigged by unwated injection of charges into this structure. This can lead to destruction of circuit parts due to overcurrent.

Latch-up rules are not checked by default. Latch-up rule checking must be switched on separately.

Latch-up Protection on Output Buffers

1. Connect source of NMOS and PMOS devices to VSS and VDD, respectively.

2. Connect drain of NMOS and PMOS devices directly to the output pad.

3. Place guard rings (VSS, VDD ties) around any NMOS and PMOS devices, which are directly tied to a pad.

4. Double guard rings (N-Well isolator and P+ isolator) should be inserted between n-channel and p- channel output buffers.

5. Double guard rings (N-Well isolator and P+ isolator) should be inserted between output buffers and internal circuit area.

I/O latch-up protection scheme.

Additional Rules for Subtrate and NWell Ties

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

LU.a & Max. space from any portion of inside to an tie &

LU.a & Max. space from any portion of inside to an tie & &

LU.b & Max. space from any portion of inside to an tie &

LU.b & Max. space from any portion of inside to an tie & &

LU.c & Max. extension of an abutted tie beyond &

LU.c & Max. extension of an abutted tie beyond & &

LU.c1 & Max. extension of an abutted substrate tie beyond &

LU.c1 & Max. extension of an abutted substrate tie beyond & &

LU.d & Max. extension of tie tie beyond &

LU.d & Max. extension of tie tie beyond & &

LU.d1 & Max. extension of an substrate tie beyond &

LU.d1 & Max. extension of an substrate tie beyond & &

Latch-up protection rules.

Metal Slits

Large areas of metal are subject to mechanical stress during production. This can cause metal detachment from the oxide. The use of metal slits leads to reduction of mechanical stress.

Metal stands for all metal layers (, and ).

Metal = + +

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Slt.a & Min. width &

Slt.a & Min. width & &

Slt.b & Max. width &

Slt.b & Max. width & &

Slt.c & Max. width without requiring a slit &

Slt.c & Max. width without requiring a slit & &

Slt.e & No slits required on bond pads &

Slt.e & No slits required on bond pads & &

Slt.e1 & No slits required on &

Slt.e1 & No slits required on & &

Slt.f & Min. enclosure of &

Slt.f & Min. enclosure of & &

Slt.g & Min. and space to &

Slt.g & Min. and space to & &

Slt.h1 & Min. space to and &

Slt.h1 & Min. space to and & &

Slt.h2 & Min. space to and &

Slt.h2 & Min. space to and & &

Slt.h3 & Min. space to and &

Slt.h3 & Min. space to and & &

Slt.h4 & Min. space to &

Slt.h4 & Min. space to & &

Slt.i & Min. density for any plate bigger than 35 µm x 35 µm [%] &

Slt.i & Min. density for any plate bigger than 35 µm x 35 µm [%] & &

Metal slits dimensions.

Pin Layer Rules

Circuit designers should use only drawing purpose 0 (data types) for layouts. Only exception is pin purpose 2 for symbolic pins. Data type 2 (purpose pin) is used for symbolic connectivity information. Pin areas must be fully covered by drawing. These rules are tested because pin areas are not used for mask generation and a potential issue due to false postive LVS matchs.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Pin.a & Min. enclosure of &

Pin.a & Min. enclosure of & & 0.00

Pin.b & Min. enclosure of &

Pin.b & Min. enclosure of & & 0.00

Pin.e & Min. enclosure of &

Pin.e & Min. enclosure of & & 0.00

Pin.f & Min. enclosure of &

Pin.f & Min. enclosure of & & 0.00

Pin.g & Min. enclosure of &

Pin.g & Min. enclosure of & & 0.00

Pin.h & Min. enclosure of &

Pin.h & Min. enclosure of & & 0.00

Rules of Digital Design

DigiBnd Layer

Digital designs can be marked with the layer. This layer must be used when using IHP’s standard digital libraries. must enclose the complete layout of the digital components. Within the layer the following design rules are changed compared to the analog flow.

NWell

Refer to section 5.1 for NWell standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

NW.c1 & Min. enclosure of inside &

NW.c1 & Min. enclosure of inside & &

NW.d1 & Min. space to external inside &

NW.d1 & Min. space to external inside & &

NW.e1 & Min. enclosure of NWell tie surrounded entirely by in inside &

NW.e1 & Min. enclosure of NWell tie surrounded entirely by in inside & &

NW.f1 & Min. space to substrate tie in inside &

NW.f1 & Min. space to substrate tie in inside & &

Cont

Refer to section 5.14 for Cont standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Cnt.c & Min. enclosure of &

Cnt.c & Min. enclosure of & &

nmosi and nmosiHV

Refer to section 6.5 for nmosi and nmosiHV standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

nmosi.e1 & A separate Iso-PWell contact unabutted to a nmosi device is not allowed &

nmosi.e1 & A separate Iso-PWell contact unabutted to a nmosi device is not allowed & &

nmosi.e2 & nmosi unabutted to an Iso-PWell-Activ tie is not allowed &

nmosi.e2 & nmosi unabutted to an Iso-PWell-Activ tie is not allowed & &

DigiSub Layer

The layer is used to define an area of a layout in which substrate contacts are extracted as a short instead of a resistive component. It is assumed that the substrate in which the components are located has the same potential as the metal connections that are connected to the substrate contact. There is no voltage drop within the substrate.

SRAM Layer

SRAM cells can be marked with the layer. must enclose the complete layout of the SRAM components. Within the layer the following design rules are changed compared to the analog flow.

NWell

Refer to section 5.1 for NWell standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

NW.c & Min. enclosure of (thin gate oxide) &

NW.c & Min. enclosure of (thin gate oxide) & &

NW.d & Min. space to external &

NW.d & Min. space to external & &

Activ

Refer to section 5.5 for Activ standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Act.c & Min. drain/source extension &

Act.c & Min. drain/source extension & &

GatPoly

Refer to section 5.8 for GatPoly standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Gat.a & Min. width &

Gat.a & Min. width & &

Gat.b & Min. space or notch &

Gat.b & Min. space or notch & &

Gat.c & Min. extension over (end cap) &

Gat.c & Min. extension over (end cap) & &

Gat.d & Min. space to &

Gat.d & Min. space to & &

pSD

Refer to section 5.10 for pSD standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

pSD.e & Min. overlap of when forming abutted substrate tie &

pSD.e & Min. overlap of when forming abutted substrate tie & &

pSD.g & Min. or width when forming abutted tie &

pSD.g & Min. or width when forming abutted tie & &

pSD.g & Min. enclosure of PFET gate (thin gate oxide) &

pSD.g & Min. enclosure of PFET gate (thin gate oxide) & &

pSD.g & Min. space to NFET gate (thin gate oxide) &

pSD.g & Min. space to NFET gate (thin gate oxide) & &

Cont

Refer to section 5.14 for Cont standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Cnt.c & Min. enclosure of &

Cnt.c & Min. enclosure of & &

Cnt.d & Min. enclosure of &

Cnt.d & Min. enclosure of & &

Cnt.f & Min. on space to &

Cnt.f & Min. on space to & &

Cnt.g2 & Min. overlap of on &

Cnt.g2 & Min. overlap of on & &

Metal1

Refer to section 5.16 for Metal1 standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

M1.b & Min. space or notch &

M1.b & Min. space or notch & &

M1.c1 & Min. endcap enclosure of &

M1.c1 & Min. endcap enclosure of & &

M1.i & Min. space of lines of which at least one is bent by 45-degree &

M1.i & Min. space of lines of which at least one is bent by 45-degree & &

Metal(n=2-5)

Refer to section 5.17 for Metal(n=2-5) standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

M1.b & Min. space or notch &

M1.b & Min. space or notch & &

M1.c1 & Min. endcap enclosure of &

M1.c1 & Min. endcap enclosure of & &

Via1

Refer to section 5.19 for Via1 standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

V1.c1 & Min. endcap enclosure of &

V1.c1 & Min. endcap enclosure of & &

Via(n=2-4)

Refer to section 5.20 for Via(n=2-4) standard rule definitions.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

Vn.c1 & Min. endcap enclosure of &

Vn.c1 & Min. endcap enclosure of & &

Localized Backside Etching (LBE)

The backside etching module is not qualified and not yet tested under all conditions. The module is not available for SG13RH.

cross-section.

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

LBE.a & Min. width &

LBE.a & Min. width & &

LBE.b & Max. width &

LBE.b & Max. width & &

LBE.b1 & Max. area (µm²) &

LBE.b1 & Max. area (µm²) & &

LBE.b2 & Min. area (µm²) &

LBE.b2 & Min. area (µm²) & &

LBE.c & Min. space or notch &

LBE.c & Min. space or notch & &

LBE.d & Min. space to inner edge of &

LBE.d & Min. space to inner edge of & &

LBE.e & Min. space to and &

LBE.e & Min. space to and & &

LBE.f & Min. space to &

LBE.f & Min. space to & &

LBE.h & No ring allowed &

LBE.h & No ring allowed & &

LBE.i & Max. global density [%] &

LBE.i & Max. global density [%] & &

dimensions.

Through-Silicon Via for Grounding (TSV_G)

The TSV_G module is not qualified and not yet tested under all conditions. Please note that wafers processed at IHP have full backside metallization.

TSV module cross-section.

Areas with etched TSV ring are recognized by the layer. No grid check is performed on layer .

|>

p2.4cm|>

p10.5cm|>p1.8cm|

& &

TSV_G.a & has to be a ring structure &

TSV_G.a & has to be a ring structure & &

TSV_G.b & Min. and max. width &

TSV_G.b & Min. and max. width & &

TSV_G.c & ring diameter &

TSV_G.c & ring diameter & &

TSV_G.d & Min. space &

TSV_G.d & Min. space & &

TSV_G.e & Min. space to , , , and &

TSV_G.e & Min. space to , , , and & &

TSV_G.f & Min. enclosure of &

TSV_G.f & Min. enclosure of & &

TSV_G.g & Min. enclosure of ring structure &

TSV_G.g & Min. enclosure of ring structure & &

TSV_G.i & Max. global density [%] &

TSV_G.i & Max. global density [%] & &

TSV_G.j & Max. coverage ratio for any 500.0 x 500.0 µm² chip area [%] &

TSV_G.j & Max. coverage ratio for any 500.0 x 500.0 µm² chip area [%] & &

TSV dimensions.

Change history

Rev. 0.1	-04-20	Initial revision
Rev. 0.2	-03-08	Document structure completely revised Add missing figures to rule sections Chapter 2: Add layer isoNWell to 257:0 Chapter 3: Add chapter “General Requirements” Chapter 3.2: Add NoDRC Chapter 4: Add chapter “Terminology” Chapter 4.2: Add introduction text, add PWell, nBuLay and Gate descriptions Chapter 5.1: Update NW.c, NW.c1, NW.d, NW.d1, NW.e, NW.e1, NW.f, NW.f1 rule descriptions, remove (old) note 3, update (old) note 4 Chapter 5.2: Update PWB.e, PWB.e1, PWB.f, PWB.f1 rule descriptions Chapter 5.3: Update introduction text, update note 1, remove note 2 Chapter 5.4: Remove note 1, move note 2 into introduction text Chapter 5.6: Remove note 2, change AFil.b to 0.42 Chapter 5.8: Move GatPoly:filler part of Gat.c to (new) GFil.j, update Gat.g description Chapter 5.9: Remove (old) Gat.j, move GatPoly:filler part of Gat.c to (new) GFil.j, remove note 2 Chapter 5.10: Add introduction text Chapter 5.14: Add introduction text Chapter 5.15: Update introduction text Chapter 5.18: Remove note 3, update note 2 text, change MFil.b to 0.42 Chapter 5.23: Add introduction text, remove note 1 Chapter 5.26: Add introduction text, remove note 1 Chapter 6.4: Update note 1 Chapter 6.6: Update introduction text, remove table containing pcell parameters Chapter 6.9: Update introduction text, update note 1 Chapter 6.9.1: Merge note 1 und note 3, move note 1 to introduction text Chapter 6.9.2: Merge note 1 und note 3, move note 1 to introduction text Chapter 6.10: Section renamed to “Sealring”, update introduction text, remove note 2 and note 4, move note 1 to introduction text, add Seal.m, update Seal.e and Seal.f descriptions Chapter 6.11: Remove MIM.i, remove “Yield Enhancement Guideline” Chapter 6.12: Rename section to “Inductors”, add explanation of the connection method, add Fig. 6.10, fix waived design rules Chapter 7: Remove section “Layer generation” (overview of generated layers can be found in section 4.2), remove section “NoDRC”, move sections “Grid Rules” and “Forbidden Layers” to chapter 3 Chapter 7.1: Move note 1 to introduction text Chapter 7.2: Add introduction text, change LU.c1 description to “Max. extention of an abutted substrate tie beyond Cont” Chapter 7.3: Update introduction text
		Chapter 8.1: Update introduction text Chapter 8.1.1: Change to subsection of section 8.1, align description to original descriptions in section 5.1 Chapter 8.1.2: Change to subsection of section 8.1 Chapter 8.1.3: Change to subsection of section 8.1 Chapter 8.2: Update introduction text Chapter 8.3: Update introduction text Chapter 10: Remove TSV_G.h, update TSV_G.g description, update Fig. 10.1

Known issues

1

as a drawing layer only valid if and are identical. E.g. rhigh resistor (see 6.4)